The pipelined ADC is a popular ADC system architecture used in a wide variety of applications including for example, digital imaging, data transmission, and wireless communications. In general, an analog input signal is sampled and held while a first stage quantizes the sample into digital bits. The digitized sample is then fed into a digital-to-analog converter, hereinafter DAC, and the resulting analog output is subtracted from the original sample. The residue thus obtained is then typically gained up by a desired gain factor and passed to a next similar stage. The process is repeated as the sample continues through additional stages of the pipeline.
The high throughput of the pipelining process is facilitated by the sample-and-hold capability embedded within each stage. Due to the sample-and-hold, as soon as a given stage finishes processing a sample, it can begin processing a subsequent sample. In most pipelined ADCs implemented with CMOS technology, the sample-and-hold is implemented along with the gain amplifier and multiplying-digital-to-analog converter (MDAC) as a single switched-capacitor capacitor circuit block. It is known in the arts to couple the output node of a sample-and-hold circuit to the following pipeline stage during certain clock phases using MOS switches. Problems exist, however, in the implementation of the switching mechanisms themselves, including the inevitable resistance of the MOS switch, which tends to vary as a function of the input voltage. As a result, settling times and harmonic distortion can be increased.
Referring to FIG. 1, a representative example of a prior art circuit 10 is shown. Two operational phases are assumed, arbitrarily denominated “phase 1” and “phase 2” for the purposes of discussion. During phase 1, switches A and B are in the “on” state and capacitor C1 charges at the input voltage. During phase 2, switch D puts the capacitor C1 into feedback mode and switch E tracks the input voltage. In operation, particularly at high frequencies, the “on” resistance of switch E creates problems, specifically settling degradation and harmonic distortion. It can be seen that during phase 1, the input of the op amp 12 is shorted to ground at switch B. Therefore, assuming zero offset, the output OUT of the opamp 12 would be expected to be zero as well. Because of offsets however, the output node OUT tends to saturate at the level of either the power supply VDD or ground rail VSS. In order to avoid this, switch F is used to connect the op amp output node OUT to ground. The circuit 10 of FIG. 1 typifies the prior art approach to alleviating the effects of the current due to amplifier offset. Those skilled in the arts will realize that the voltage at the output node OUT′ is controlled in some way during phase 1. For example, in a 1.5 bit per stage pipeline, the output node OUT′ is controlled by a multiplying-digital-to-analog Converter (MDAC) 14.
Efforts to address the problems of non-linear switch resistance can lead to often increasingly complex switch bootstrapping arrangements, which require further implementation tradeoffs between increased circuit area and increased parasitic capacitances. Due to these and other problems, improved circuits and methods for implementing sample-and-hold functions in pipelined ADCs would be useful and advantageous in the arts.